

##############################################
##########      Configuration       ##########
##############################################
#set_property CONFIG_VOLTAGE 1.8 [current_design]
#set_property CONFIG_MODE SPIx4 [current_design]
# Bitstream configuration settings
#set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
#set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
# Must set to "NO" if loading from backup flash partition
#set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
#set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]
#set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]



###############################################
###########           LEDs           ##########
###############################################
# Active Low Led 0
set_property IOSTANDARD LVCMOS12 [get_ports {leds[0]}]
set_property PACKAGE_PIN AR19 [get_ports {leds[0]}]
# Active Low Led 1
set_property IOSTANDARD LVCMOS12 [get_ports {leds[1]}]
set_property PACKAGE_PIN AT17 [get_ports {leds[1]}]
# Active Low Led 2
set_property IOSTANDARD LVCMOS12 [get_ports {leds[2]}]
set_property PACKAGE_PIN AR17 [get_ports {leds[2]}]
# Active Low Led 3
set_property IOSTANDARD LVCMOS12 [get_ports {leds[3]}]
set_property PACKAGE_PIN AU19 [get_ports {leds[3]}]

set_property IOSTANDARD LVCMOS12 [get_ports {leds[4]}]
set_property PACKAGE_PIN AU20 [get_ports {leds[4]}]
# Active Low Led 1
set_property IOSTANDARD LVCMOS12 [get_ports {leds[5]}]
set_property PACKAGE_PIN AW21 [get_ports {leds[5]}]
# Active Low Led 2
set_property IOSTANDARD LVCMOS12 [get_ports {leds[6]}]
set_property PACKAGE_PIN AV21 [get_ports {leds[6]}]
# Active Low Led 3
set_property IOSTANDARD LVCMOS12 [get_ports {leds[7]}]
set_property PACKAGE_PIN AV17 [get_ports {leds[7]}]

##############################################
##########           PCIe           ##########
##############################################
#set_property PACKAGE_PIN AY23 [get_ports progclk_b1_p]
#set_property PACKAGE_PIN BA23 [get_ports progclk_b1_n]
#set_property IOSTANDARD DIFF_SSTL18_I [get_ports progclk_b1_p]
# PCIE Active Low Reset

set_property PACKAGE_PIN AU1 [get_ports sys_reset_n]
set_property IOSTANDARD LVCMOS18 [get_ports sys_reset_n]
set_property PULLUP true [get_ports sys_reset_n]
set_false_path -from [get_ports sys_reset_n]

# PCIE Reference Clock 0
set_property PACKAGE_PIN U34 [get_ports {sys_clk_n[0]}]
set_property PACKAGE_PIN U33 [get_ports {sys_clk_p[0]}]

create_clock -period 10.000 -name sys_clk0 [get_ports {sys_clk_p[0]}]

#set_property PACKAGE_PIN H31  [get_ports {pcie_txp[0]}]
#set_property PACKAGE_PIN H32  [get_ports {pcie_txn[0]}]
#set_property PACKAGE_PIN J38  [get_ports {pcie_rxp[0]}]
#set_property PACKAGE_PIN J39  [get_ports {pcie_rxn[0]}]

#set_property PACKAGE_PIN G33  [get_ports {pcie_txp[1]}]
#set_property PACKAGE_PIN G34  [get_ports {pcie_txn[1]}]
#set_property PACKAGE_PIN H36  [get_ports {pcie_rxp[1]}]
#set_property PACKAGE_PIN H37  [get_ports {pcie_rxn[1]}]

#set_property PACKAGE_PIN F31  [get_ports {pcie_txp[2]}]
#set_property PACKAGE_PIN F32  [get_ports {pcie_txn[2]}]
#set_property PACKAGE_PIN G38  [get_ports {pcie_rxp[2]}]
#set_property PACKAGE_PIN G39  [get_ports {pcie_rxn[2]}]

#set_property PACKAGE_PIN E33  [get_ports {pcie_txp[3]}]
#set_property PACKAGE_PIN E34  [get_ports {pcie_txn[3]}]
#set_property PACKAGE_PIN F36  [get_ports {pcie_rxp[3]}]
#set_property PACKAGE_PIN F37  [get_ports {pcie_rxn[3]}]

#set_property PACKAGE_PIN D31 [get_ports {pcie_txp[4]}]
#set_property PACKAGE_PIN D32 [get_ports {pcie_txn[4]}]
#set_property PACKAGE_PIN E38 [get_ports {pcie_rxp[4]}]
#set_property PACKAGE_PIN E39 [get_ports {pcie_rxn[4]}]

#set_property PACKAGE_PIN C33 [get_ports {pcie_txp[5]}]
#set_property PACKAGE_PIN C34 [get_ports {pcie_txn[5]}]
#set_property PACKAGE_PIN D36 [get_ports {pcie_rxp[5]}]
#set_property PACKAGE_PIN D37 [get_ports {pcie_rxn[5]}]

#set_property PACKAGE_PIN B31 [get_ports {pcie_txp[6]}]
#set_property PACKAGE_PIN B32 [get_ports {pcie_txn[6]}]
#set_property PACKAGE_PIN C38 [get_ports {pcie_rxp[6]}]
#set_property PACKAGE_PIN C39 [get_ports {pcie_rxn[6]}]

#set_property PACKAGE_PIN A33 [get_ports {pcie_txp[7]}]
#set_property PACKAGE_PIN A34 [get_ports {pcie_txn[7]}]
#set_property PACKAGE_PIN B36 [get_ports {pcie_rxp[7]}]
#set_property PACKAGE_PIN B37 [get_ports {pcie_rxn[7]}]

#PL_I2C1_SDA_LS
set_property PACKAGE_PIN K12 [get_ports SDA]
set_property IOSTANDARD LVCMOS12 [get_ports SDA]
set_property DRIVE 8 [get_ports SDA]
#PL_I2C1_SCL_LS
set_property PACKAGE_PIN G10 [get_ports SCL]
set_property IOSTANDARD LVCMOS12 [get_ports SCL]
set_property DRIVE 8 [get_ports SCL]

#set_property PACKAGE_PIN A26 [get_ports {i2cmux_rst}]
#set_property IOSTANDARD LVCMOS18 [get_ports {i2cmux_rst}]


#ENET_CLKOUT
#set_property PACKAGE_PIN AA29 [get_ports emcclk]
#set_property IOSTANDARD LVCMOS18 [get_ports emcclk]
